The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM IN, body_height: 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM IN, body_length: 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND LOW POWER AND W/TOTEM POLE OUTPUT, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, precious_material: GOLD. This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-137-5060, indicating validated use in U.S.
government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels. Verify compatibility with your specific system configuration before ordering.
| body_width | 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM IN |
| body_height | 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM IN |
| body_length | 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM IN |
| features_provided | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND LOW POWER AND W/TOTEM POLE OUTPUT |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| precious_material | GOLD |
| inclosure_material | GLASS AND METAL |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | DUAL 2 WIDE 2-3 INPUT |
| inclosure_configuration | FLAT PACK |
| terminal_surface_treatment | SOLDER |
| NSN | 5962-00-137-5060 |
| PRECIOUS MATERIAL | GOLD |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, AND-OR INVERT |
| INCLOSURE MATERIAL | GLASS AND METAL |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND LOW POWER AND W/TOTEM POLE OUTPUT |
| INPUT CIRCUIT PATTERN | DUAL 2 WIDE 2-3 INPUT |
| PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD AND BODY GOLD |
| TEST DATA DOCUMENT | 13499-351-7365 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |