The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN, body_height: 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN, body_length: 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN, features_provided: MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND LOW LEVEL AND MEDIUM SPEED, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC AND GLASS. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-352-9361, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| body_height | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| body_length | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| features_provided | MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND LOW LEVEL AND MEDIUM SPEED |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC AND GLASS |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| test_data_document | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | TRIPLE 3 INPUT |
| inclosure_configuration | DUAL-IN-LINE |
| terminal_surface_treatment | SOLDER |
| NSN | 5962-00-352-9361 |
| MAXIMUM POWER DISSIPATION RATING | 10.0 MILLIWATTS |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| TIME RATING PER CHACTERISTIC | 13.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| DESIGN FUNCTION AND QUANTITY | 3 GATE, NAND |
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS DEGC |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND LOW LEVEL AND MEDIUM SPEED |