RECEIVER-TRANSMITTER SUBASSEMBLY. Key specifications include body_width: 0.252 INCHES MINIMUM AND 0.290 INCHES MAXIMUM IN, body_height: 0.115 INCHES MINIMUM AND 0.125 INCHES MAXIMUM IN, body_length: 0.745 INCHES MINIMUM AND 0.755 INCHES MAXIMUM IN, bit_quantity: 256, overall_width: 5.180 INCHES NOMINAL IN, word_quantity: 32. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-139-4243, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.252 INCHES MINIMUM AND 0.290 INCHES MAXIMUM IN |
| body_height | 0.115 INCHES MINIMUM AND 0.125 INCHES MAXIMUM IN |
| body_length | 0.745 INCHES MINIMUM AND 0.755 INCHES MAXIMUM IN |
| bit_quantity | 256 |
| overall_width | 5.180 INCHES NOMINAL IN |
| word_quantity | 32 |
| overall_height | 5.313 INCHES NOMINAL IN |
| overall_length | 17.130 INCHES NOMINAL IN |
| features_provided | PROGRAMMABLE AND BIPOLAR AND 3-STATE OUTPUT AND W/ENABLE |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | PLASTIC |
| memory_device_type | ROM |
| NSN | 5962-01-139-4243 |
| OPERATING TEMP RANGE | +0.0 TO 75.0 CELSIUS DEGC |
| TERMINAL SURFACE TREATMENT | SOLDER |
| BIT QUANTITY | 256 |
| BODY WIDTH | 0.252 INCHES MINIMUM AND 0.290 INCHES MAXIMUM IN |
| INPUT CIRCUIT PATTERN | 6 INPUT |
| TIME RATING PER CHACTERISTIC | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| INCLOSURE MATERIAL | PLASTIC |
| FEATURES PROVIDED | PROGRAMMABLE AND BIPOLAR AND 3-STATE OUTPUT AND W/ENABLE |