The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.280 INCHES MAXIMUM IN, body_height: 0.180 INCHES MAXIMUM IN, body_length: 0.785 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED AND BURN IN AND W/TOTEM POLE OUTPUT AND POSITIVE OUTPUTS, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-093-8234, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.280 INCHES MAXIMUM IN |
| body_height | 0.180 INCHES MAXIMUM IN |
| body_length | 0.785 INCHES MAXIMUM IN |
| features_provided | HERMETICALLY SEALED AND BURN IN AND W/TOTEM POLE OUTPUT AND POSITIVE OUTPUTS |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| test_data_document | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| operating_temp_range | +0.0 TO 70.0 CELSIUS DEGC |
| input_circuit_pattern | DUAL 4 INPUT |
| inclosure_configuration | DUAL-IN-LINE |
| terminal_surface_treatment | SOLDER |
| NSN | 5962-01-093-8234 |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| MAXIMUM POWER DISSIPATION RATING | 22.0 MILLIWATTS |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| FEATURES PROVIDED | HERMETICALLY SEALED AND BURN IN AND W/TOTEM POLE OUTPUT AND POSITIVE OUTPUTS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| TERMINAL SURFACE TREATMENT | SOLDER |
| CASE OUTLINE SOURCE AND DESIGNATOR | TO-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| BODY LENGTH | 0.785 INCHES MAXIMUM IN |
| TIME RATING PER CHACTERISTIC | 12.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 12.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, AND |