The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM IN, body_height: 0.185 INCHES MAXIMUM IN, body_length: 0.796 INCHES MAXIMUM IN, features_provided: MONOLITHIC, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-041-3494, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM IN |
| body_height | 0.185 INCHES MAXIMUM IN |
| body_length | 0.796 INCHES MAXIMUM IN |
| features_provided | MONOLITHIC |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | QUAD 2 INPUT |
| end_item_identification | 5820-01-084-2444 RADAR SET |
| inclosure_configuration | DUAL-IN-LINE |
| terminal_surface_treatment | SOLDER |
| NSN | 5962-01-041-3494 |
| BODY HEIGHT | 0.180 INCHES MAXIMUM IN |
| TIME RATING PER CHACTERISTIC | 5.50 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 5.50 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS DEGC |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS DEGC |
| TEST DATA DOCUMENT | 80063-SM-A-699713 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |