Name: MICROCIRCUIT,DIGITAL
Brand: Unknown
SKU: SN74LS373J

SN74LS373J ✓ Verified by PartsTable

— · COMPONENT

WHAT YOU NEED TO KNOW

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PRODUCT OVERVIEW

The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM IN, body_height: 0.200 INCHES MAXIMUM IN, body_length: 1.060 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED AND MONOLITHIC AND W/CLOCK AND W/RESET AND BURN IN, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: SILICON. This product is currently in active production with full OEM support.

This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-100-7300, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.

Verify compatibility with your specific system configuration before ordering.

WHERE IT FITS

SN74LS373J

NSN: 5962-01-100-7300
FSC: 5962
CAGE: 01295 — TEXAS INSTRUMENTS INCORPORATED (USA)

SPECIFICATIONS

body_width	0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM IN
body_height	0.200 INCHES MAXIMUM IN
body_length	1.060 INCHES MAXIMUM IN
features_provided	HERMETICALLY SEALED AND MONOLITHIC AND W/CLOCK AND W/RESET AND BURN IN
output_logic_form	TRANSISTOR-TRANSISTOR LOGIC
inclosure_material	SILICON
storage_temp_range	-65.0 TO 150.0 CELSIUS DEGC
operating_temp_range	-55.0 TO 125.0 CELSIUS DEGC
body_outside_diameter	0.290 INCHES MINIMUM AND 0.320 INCHES MAXIMUM IN
input_circuit_pattern	14 INPUT
inclosure_configuration	DUAL-IN-LINE
terminal_surface_treatment	SOLDER
NSN	5962-01-100-7300

COMPONENT DIAGRAM

KEY FEATURES

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TEST DATA DOCUMENT: 16331-63A133588 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)

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INPUT CIRCUIT PATTERN: 10 INPUT

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OUTPUT LOGIC FORM: TRANSISTOR-TRANSISTOR LOGIC

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TIME RATING PER CHACTERISTIC: 28.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 28.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS

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INCLOSURE MATERIAL: CERAMIC AND GLASS

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DESIGN FUNCTION AND QUANTITY: 8 LATCH, D

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OPERATING TEMP RANGE: +0.0 TO 70.0 CELSIUS DEGC

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STORAGE TEMP RANGE: -65.0 TO 150.0 CELSIUS DEGC

TECHNICAL CHARACTERISTICS (FLIS)

TEST DATA DOCUMENT	16331-63A133588 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)
INPUT CIRCUIT PATTERN	10 INPUT
OUTPUT LOGIC FORM	TRANSISTOR-TRANSISTOR LOGIC
TIME RATING PER CHACTERISTIC	28.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 28.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS
INCLOSURE MATERIAL	CERAMIC AND GLASS
DESIGN FUNCTION AND QUANTITY	8 LATCH, D
OPERATING TEMP RANGE	+0.0 TO 70.0 CELSIUS DEGC
STORAGE TEMP RANGE	-65.0 TO 150.0 CELSIUS DEGC
BODY WIDTH	0.240 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN
BODY HEIGHT	0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN

VERIFIED SUBSTITUTES & CROSS-REFERENCES 7

Z80A-CPUInterchangeable