The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.245 INCHES MINIMUM AND 0.300 INCHES MAXIMUM IN, body_height: 0.120 INCHES MINIMUM AND 0.195 INCHES MAXIMUM IN, body_length: 0.750 INCHES MINIMUM AND 0.795 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND W/ENABLE AND COMPLEMENTARY OUTPUTS, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC AND GLASS. This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-403-4530, indicating validated use in U.S.
government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels. Verify compatibility with your specific system configuration before ordering.
| body_width | 0.245 INCHES MINIMUM AND 0.300 INCHES MAXIMUM IN |
| body_height | 0.120 INCHES MINIMUM AND 0.195 INCHES MAXIMUM IN |
| body_length | 0.750 INCHES MINIMUM AND 0.795 INCHES MAXIMUM IN |
| features_provided | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND W/ENABLE AND COMPLEMENTARY OUTPUTS |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC AND GLASS |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | +0.0 TO 70.0 CELSIUS DEGC |
| input_circuit_pattern | 6 INPUT |
| inclosure_configuration | DUAL-IN-LINE |
| design_function_and_quantity | 4 LATCH, D |
| time_rating_per_chacteristic | 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 25.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| NSN | 5962-00-403-4530 |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 6 INPUT |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| MAXIMUM POWER DISSIPATION RATING | 280.0 MILLIWATTS |
| TIME RATING PER CHACTERISTIC | 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 25.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| CASE OUTLINE SOURCE AND DESIGNATOR | -0-001-AG JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 4 LATCH, D |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| BODY HEIGHT | 0.120 INCHES MINIMUM AND 0.195 INCHES MAXIMUM IN |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND W/ENABLE AND COMPLEMENTARY OUTPUTS |