The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.260 INCHES MAXIMUM IN, body_height: 0.062 INCHES MAXIMUM IN, body_length: 0.350 INCHES MAXIMUM IN, overall_height: 0.400 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-147-4456, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.260 INCHES MAXIMUM IN |
| body_height | 0.062 INCHES MAXIMUM IN |
| body_length | 0.350 INCHES MAXIMUM IN |
| overall_height | 0.400 INCHES MAXIMUM IN |
| features_provided | HERMETICALLY SEALED |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | GLASS |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | -0.0 TO 70.0 CELSIUS DEGC |
| input_circuit_pattern | TRIPLE 3 INPUT |
| end_item_identification | H-46 HELO |
| inclosure_configuration | FLAT PACK |
| NSN | 5962-00-147-4456 |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| TEST DATA DOCUMENT | 00752-373405 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| MAXIMUM POWER DISSIPATION RATING | 120.0 MILLIWATTS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS DEGC |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TIME RATING PER CHACTERISTIC | 22.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| INPUT CIRCUIT PATTERN | TRIPLE 3 INPUT |
| DESIGN FUNCTION AND QUANTITY | 3 GATE, NAND |