The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN, body_height: 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN, body_length: 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN, features_provided: MONOLITHIC AND POSITIVE OUTPUTS AND EDGE TRIGGERED AND PRESETTABLE AND W/CLEAR, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, precious_material: SILVER. This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-437-8207, indicating validated use in U.S.
government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels. Verify compatibility with your specific system configuration before ordering.
| body_width | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| body_height | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| body_length | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| features_provided | MONOLITHIC AND POSITIVE OUTPUTS AND EDGE TRIGGERED AND PRESETTABLE AND W/CLEAR |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| precious_material | SILVER |
| inclosure_material | PLASTIC |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | +0.0 TO 70.0 CELSIUS DEGC |
| input_circuit_pattern | 9 INPUT |
| inclosure_configuration | DUAL-IN-LINE |
| design_function_and_quantity | 1 FLIP-FLOP, CLOCKED AND 1 FLIP-FLOP, J-K, AND INPUT MASTER SLAVE |
| NSN | 5962-00-437-8207 |
| FEATURES PROVIDED | MONOLITHIC AND POSITIVE OUTPUTS AND EDGE TRIGGERED AND PRESETTABLE AND W/CLEAR |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| OPERATING TEMP RANGE | +0.0 TO 70.0 CELSIUS DEGC |
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| INPUT CIRCUIT PATTERN | 9 INPUT |
| PRECIOUS MATERIAL AND LOCATION | TERMINALS SILVER |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, CLOCKED AND 1 FLIP-FLOP, J-K, AND INPUT MASTER SLAVE |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |