The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM IN, body_height: 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM IN, body_length: 0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM IN, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC AND GLASS, storage_temp_range: -65.0 TO 150.0 CELSIUS DEGC. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-469-5876, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM IN |
| body_height | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM IN |
| body_length | 0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM IN |
| features_provided | MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND HIGH SPEED AND W/ENABLE AND NEGATIVE EDGE TRIGGERED AND PRESETTABLE AND RESETTABLE |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC AND GLASS |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | 10 INPUT |
| inclosure_configuration | FLAT PACK |
| design_function_and_quantity | 1 FLIP-FLOP, CLOCKED AND 1 FLIP-FLOP, J-K, AND INPUT |
| time_rating_per_chacteristic | 11.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 9.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| NSN | 5962-00-469-5876 |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM IN |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND HIGH SPEED AND W/ENABLE AND NEGATIVE EDGE TRIGGERED AND PRESETTABLE AND RESETTABLE |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS DEGC |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM IN |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-86 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, CLOCKED AND 1 FLIP-FLOP, J-K, AND INPUT |
| INPUT CIRCUIT PATTERN | 10 INPUT |
| TIME RATING PER CHACTERISTIC | 11.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 9.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |