The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.265 INCHES MAXIMUM IN, body_height: 0.050 INCHES MINIMUM AND 0.080 INCHES MAXIMUM IN, body_length: 0.350 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED AND BURN IN AND W/TOTEM POLE OUTPUT AND LOW POWER AND SCHOTTKY, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-193-6038, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.265 INCHES MAXIMUM IN |
| body_height | 0.050 INCHES MINIMUM AND 0.080 INCHES MAXIMUM IN |
| body_length | 0.350 INCHES MAXIMUM IN |
| features_provided | HERMETICALLY SEALED AND BURN IN AND W/TOTEM POLE OUTPUT AND LOW POWER AND SCHOTTKY |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| test_data_document | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | DUAL 2 WIDE 2-3 INPUT |
| inclosure_configuration | FLAT PACK |
| terminal_surface_treatment | SOLDER |
| NSN | 5962-01-193-6038 |
| BODY WIDTH | 0.265 INCHES MAXIMUM IN |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 7.0 VOLTS MAXIMUM POWER SOURCE |
| TIME RATING PER CHACTERISTIC | 20.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 20.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| INCLOSURE MATERIAL | CERAMIC |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, AND-OR INVERT |
| INCLOSURE CONFIGURATION | FLAT PACK |
| TERMINAL SURFACE TREATMENT | SOLDER |
| BODY LENGTH | 0.350 INCHES MAXIMUM IN |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |