The MICROCIRCUIT,MEMORY is a the manufacturer memory module engineered for enterprise server and workstation platforms requiring validated, high-reliability memory. Key specifications include body_width: 0.355 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN, body_height: 0.090 INCHES MAXIMUM IN, body_length: 0.355 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: GLASS AND METAL, memory_device_type: ROM. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-123-3179, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.355 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN |
| body_height | 0.090 INCHES MAXIMUM IN |
| body_length | 0.355 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN |
| features_provided | HERMETICALLY SEALED AND MONOLITHIC AND BIPOLAR AND BURN IN, MIL-STD-883, CLASS B AND ELECTROSTATIC SENSITIVE AND PROGRAMMABLE AND W/BUFFERED OUTPUT AND 3-STATE OUTPUT |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | GLASS AND METAL |
| memory_device_type | ROM |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | 12 INPUT |
| inclosure_configuration | FLAT PACK |
| terminal_surface_treatment | SOLDER |
| NSN | 5962-01-123-3179 |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INPUT CIRCUIT PATTERN | 12 INPUT |
| TERMINAL SURFACE TREATMENT | SOLDER |
| MEMORY DEVICE TYPE | ROM |
| TERMINAL TYPE AND QUANTITY | 18 FLAT LEADS |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| TIME RATING PER CHACTERISTIC | 75.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 75.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| TEST DATA DOCUMENT | 82577-932883 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| BODY WIDTH | 0.355 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |