The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM IN, body_height: 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM IN, body_length: 0.337 INCHES MINIMUM AND 0.350 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND MEDIUM POWER AND MEDIUM SPEED AND EDGE TRIGGERED AND W/CLEAR, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC AND GLASS. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-350-8395, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM IN |
| body_height | 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM IN |
| body_length | 0.337 INCHES MINIMUM AND 0.350 INCHES MAXIMUM IN |
| features_provided | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND MEDIUM POWER AND MEDIUM SPEED AND EDGE TRIGGERED AND W/CLEAR |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC AND GLASS |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | DUAL 4 INPUT |
| inclosure_configuration | FLAT PACK |
| design_function_and_quantity | 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
| time_rating_per_chacteristic | 39.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| NSN | 5962-00-350-8395 |
| MAXIMUM POWER DISSIPATION RATING | 220.0 MILLIWATTS |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND MEDIUM POWER AND MEDIUM SPEED AND EDGE TRIGGERED AND W/CLEAR |
| CASE OUTLINE SOURCE AND DESIGNATOR | -0-004-AA JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| BODY WIDTH | 0.200 INCHES MINIMUM AND 0.300 INCHES MAXIMUM IN |
| BODY LENGTH | 0.337 INCHES MINIMUM AND 0.350 INCHES MAXIMUM IN |
| TIME RATING PER CHACTERISTIC | 39.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| BODY HEIGHT | 0.008 INCHES MINIMUM AND 0.100 INCHES MAXIMUM IN |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
| TEST DATA DOCUMENT | 80249-911252 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |