91375612 — Technical Data Sheet

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— · COMPONENT

WHAT YOU NEED TO KNOW

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PRODUCT OVERVIEW

The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include BODY WIDTH: 0.310 INCHES MAXIMUM IN, BODY HEIGHT: 0.180 INCHES MAXIMUM IN, BODY LENGTH: 0.785 INCHES MAXIMUM IN, FEATURES PROVIDED: MONOLITHIC AND HERMETICALLY SEALED, OUTPUT LOGIC FORM: TRANSISTOR-TRANSISTOR LOGIC, INCLOSURE MATERIAL: CERAMIC. This product is currently in active production with full OEM support.

This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-172-8603, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.

Verify compatibility with your specific system configuration before ordering.

WHERE IT FITS

91375612

NSN: 5962-01-172-8603
FSC: 5962
CAGE: F9111 — THALES AVS FRANCE SAS (FRA)

SPECIFICATIONS

BODY WIDTH	0.310 INCHES MAXIMUM IN
BODY HEIGHT	0.180 INCHES MAXIMUM IN
BODY LENGTH	0.785 INCHES MAXIMUM IN
FEATURES PROVIDED	MONOLITHIC AND HERMETICALLY SEALED
OUTPUT LOGIC FORM	TRANSISTOR-TRANSISTOR LOGIC
INCLOSURE MATERIAL	CERAMIC
STORAGE TEMP RANGE	-65.0 TO 105.0 CELSIUS DEGC
OPERATING TEMP RANGE	-55.0 TO 125.0 CELSIUS DEGC
INPUT CIRCUIT PATTERN	6 INPUT
INCLOSURE CONFIGURATION	DUAL-IN-LINE
TERMINAL SURFACE TREATMENT	SOLDER
TERMINAL TYPE AND QUANTITY	16 PRINTED CIRCUIT
NSN	5962-01-172-8603

COMPONENT DIAGRAM

KEY FEATURES

•

INCLOSURE CONFIGURATION: DUAL-IN-LINE

•

OUTPUT LOGIC FORM: TRANSISTOR-TRANSISTOR LOGIC

•

BODY HEIGHT: 0.180 INCHES MAXIMUM IN

•

STORAGE TEMP RANGE: -65.0 TO 105.0 CELSIUS DEGC

•

TIME RATING PER CHACTERISTIC: 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS

•

DESIGN FUNCTION AND QUANTITY: 1 LATCH, ADDRESSABLE

•

TERMINAL TYPE AND QUANTITY: 16 PRINTED CIRCUIT

•

TERMINAL SURFACE TREATMENT: SOLDER

TECHNICAL CHARACTERISTICS (FLIS)

INCLOSURE CONFIGURATION	DUAL-IN-LINE
OUTPUT LOGIC FORM	TRANSISTOR-TRANSISTOR LOGIC
BODY HEIGHT	0.180 INCHES MAXIMUM IN
STORAGE TEMP RANGE	-65.0 TO 105.0 CELSIUS DEGC
TIME RATING PER CHACTERISTIC	35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS
DESIGN FUNCTION AND QUANTITY	1 LATCH, ADDRESSABLE
TERMINAL TYPE AND QUANTITY	16 PRINTED CIRCUIT
TERMINAL SURFACE TREATMENT	SOLDER
TEST DATA DOCUMENT	13499-351-7793 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)
VOLTAGE RATING AND TYPE PER CHARACTERISTIC	7.0 VOLTS MAXIMUM POWER SOURCE

VERIFIED SUBSTITUTES & CROSS-REFERENCES 12

9334DMInterchangeable