Name: MICROCIRCUIT,DIGITAL
Brand: Unknown
SKU: 6088909-1

6088909-1 ✓ Verified by PartsTable

— · COMPONENT

WHAT YOU NEED TO KNOW

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PRODUCT OVERVIEW

The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.247 INCHES MINIMUM AND 0.285 INCHES MAXIMUM IN, body_height: 0.050 INCHES MINIMUM AND 0.080 INCHES MAXIMUM IN, body_length: 0.371 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN, overall_width: 0.940 INCHES MINIMUM AND 0.960 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED AND BURN IN AND W/CLOCK AND COMPLEMENTARY OUTPUTS, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC. This product is currently in active production with full OEM support.

This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-046-3626, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.

Verify compatibility with your specific system configuration before ordering.

WHERE IT FITS

6088909-1

NSN: 5962-01-046-3626
FSC: 5962
CAGE: 09205 — LOCKHEED MARTIN CORP ELECTRONICS AND MISSILES DIV (USA)

SPECIFICATIONS

body_width	0.247 INCHES MINIMUM AND 0.285 INCHES MAXIMUM IN
body_height	0.050 INCHES MINIMUM AND 0.080 INCHES MAXIMUM IN
body_length	0.371 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN
overall_width	0.940 INCHES MINIMUM AND 0.960 INCHES MAXIMUM IN
features_provided	HERMETICALLY SEALED AND BURN IN AND W/CLOCK AND COMPLEMENTARY OUTPUTS
output_logic_form	TRANSISTOR-TRANSISTOR LOGIC
inclosure_material	CERAMIC
storage_temp_range	-65.0 TO 150.0 CELSIUS DEGC
operating_temp_range	-55.0 TO 125.0 CELSIUS DEGC
input_circuit_pattern	12 INPUT
inclosure_configuration	FLAT PACK
terminal_surface_treatment	SOLDER
NSN	5962-01-046-3626

COMPONENT DIAGRAM

KEY FEATURES

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BODY HEIGHT: 0.050 INCHES MINIMUM AND 0.080 INCHES MAXIMUM IN

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TEST DATA DOCUMENT: 03640-6088909 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)

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TERMINAL SURFACE TREATMENT: SOLDER

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DESIGN FUNCTION AND QUANTITY: 1 SHIFT REGISTER, PARALLEL LOAD

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TIME RATING PER CHACTERISTIC: 31.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS

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BODY LENGTH: 0.371 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN

•

INPUT CIRCUIT PATTERN: 12 INPUT

TECHNICAL CHARACTERISTICS (FLIS)

BODY HEIGHT	0.050 INCHES MINIMUM AND 0.080 INCHES MAXIMUM IN
TEST DATA DOCUMENT	03640-6088909 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING)
TERMINAL SURFACE TREATMENT	SOLDER
DESIGN FUNCTION AND QUANTITY	1 SHIFT REGISTER, PARALLEL LOAD
TIME RATING PER CHACTERISTIC	31.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS
OVERALL WIDTH	0.940 INCHES MINIMUM AND 0.960 INCHES MAXIMUM IN
BODY LENGTH	0.371 INCHES MINIMUM AND 0.400 INCHES MAXIMUM IN
INPUT CIRCUIT PATTERN	12 INPUT
OUTPUT LOGIC FORM	TRANSISTOR-TRANSISTOR LOGIC
OPERATING TEMP RANGE	-55.0 TO 125.0 CELSIUS DEGC

VERIFIED SUBSTITUTES & CROSS-REFERENCES 7

14741Interchangeable