The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN, body_height: 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN, body_length: 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN, features_provided: MONOLITHIC AND HERMETICALLY SEALED AND EDGE TRIGGERED AND MEDIUM SPEED AND POSITIVE OUTPUTS AND W/CLEAR AND W/ENABLE, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC AND GLASS. This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-160-5028, indicating validated use in U.S.
government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels. Verify compatibility with your specific system configuration before ordering.
| body_width | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| body_height | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| body_length | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| features_provided | MONOLITHIC AND HERMETICALLY SEALED AND EDGE TRIGGERED AND MEDIUM SPEED AND POSITIVE OUTPUTS AND W/CLEAR AND W/ENABLE |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC AND GLASS |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| test_data_document | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | DUAL 4 INPUT |
| inclosure_configuration | DUAL-IN-LINE |
| design_function_and_quantity | 2 FLIP-FLOP, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
| NSN | 5962-00-160-5028 |
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
| TIME RATING PER CHACTERISTIC | 25.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS DEGC |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |