The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN, body_height: 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN, body_length: 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC AND GLASS, storage_temp_range: -65.0 TO 150.0 CELSIUS DEGC. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-247-3396, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| body_height | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| body_length | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| features_provided | COMPLEMENTARY OUTPUTS AND EDGE TRIGGERED AND HERMETICALLY SEALED AND HIGH SPEED AND MONOLITHIC AND POSITIVE OUTPUTS AND PRESETTABLE AND W/CLEAR AND W/ENABLE |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC AND GLASS |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | DUAL 4 INPUT |
| inclosure_configuration | DUAL-IN-LINE |
| design_function_and_quantity | 2 FLIP-FLOP, D-TYPE |
| time_rating_per_chacteristic | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| NSN | 5962-00-247-3396 |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| TIME RATING PER CHACTERISTIC | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| TEST DATA DOCUMENT | 80063-SM-B-641496 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |