The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.250 INCHES NOMINAL IN, body_height: 0.180 INCHES MAXIMUM IN, body_length: 0.710 INCHES MINIMUM AND 0.770 INCHES MAXIMUM IN, features_provided: W/TOTEM POLE OUTPUT AND BURN IN AND W/RESISTOR AND POSITIVE OUTPUTS, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, precious_material: SILVER. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-614-3968, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.250 INCHES NOMINAL IN |
| body_height | 0.180 INCHES MAXIMUM IN |
| body_length | 0.710 INCHES MINIMUM AND 0.770 INCHES MAXIMUM IN |
| features_provided | W/TOTEM POLE OUTPUT AND BURN IN AND W/RESISTOR AND POSITIVE OUTPUTS |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| precious_material | SILVER |
| inclosure_material | PLASTIC |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | +0.0 TO 70.0 CELSIUS DEGC |
| input_circuit_pattern | QUAD 2 INPUT |
| inclosure_configuration | DUAL-IN-LINE |
| design_function_and_quantity | 4 GATE, AND |
| NSN | 5962-00-614-3968 |
| INCLOSURE MATERIAL | PLASTIC |
| INPUT CIRCUIT PATTERN | QUAD 2 INPUT |
| PRECIOUS MATERIAL | SILVER |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS DEGC |
| TEST DATA DOCUMENT | 50804-752-311009 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| BODY LENGTH | 0.710 INCHES MINIMUM AND 0.770 INCHES MAXIMUM IN |
| BODY WIDTH | 0.250 INCHES NOMINAL IN |
| TIME RATING PER CHACTERISTIC | 27.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 19.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |