The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN, body_height: 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN, body_length: 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: PLASTIC, storage_temp_range: -65.0 TO 150.0 CELSIUS DEGC. This product is currently in active production with full OEM support.
This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-00-420-1655, indicating validated use in U.S. government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels.
Verify compatibility with your specific system configuration before ordering.
| body_width | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| body_height | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| body_length | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| features_provided | MONOLITHIC AND POSITIVE OUTPUTS AND W/ENABLE AND ASYNCHRONOUS AND HIGH SPEED AND W/CLEAR AND HIGH GAIN AND EDGE TRIGGERED |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | PLASTIC |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | +0.0 TO 70.0 CELSIUS DEGC |
| input_circuit_pattern | DUAL 4 INPUT |
| inclosure_configuration | DUAL-IN-LINE |
| design_function_and_quantity | 2 FLIP-FLOP, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
| time_rating_per_chacteristic | 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 45.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| NSN | 5962-00-420-1655 |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| MAXIMUM POWER DISSIPATION RATING | 90.0 MILLIWATTS |
| FEATURES PROVIDED | MONOLITHIC AND POSITIVE OUTPUTS AND W/ENABLE AND ASYNCHRONOUS AND HIGH SPEED AND W/CLEAR AND HIGH GAIN AND EDGE TRIGGERED |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
| TIME RATING PER CHACTERISTIC | 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 45.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT NS |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS DEGC |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |