The MICROCIRCUIT,DIGITAL is a the manufacturer industrial component. Key specifications include body_width: 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN, body_height: 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN, body_length: 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN, features_provided: HERMETICALLY SEALED AND MONOLITHIC AND NEGATIVE OUTPUTS AND POSITIVE OUTPUTS AND DC COUPLED, output_logic_form: TRANSISTOR-TRANSISTOR LOGIC, inclosure_material: CERAMIC AND GLASS. This part is cataloged in the Federal Logistics Information System (FLIS) under NSN 5962-01-034-3875, indicating validated use in U.S.
government and defense logistics supply chains. Available through authorized enterprise resellers and TPM (Third Party Maintenance) channels. Verify compatibility with your specific system configuration before ordering.
| body_width | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM IN |
| body_height | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM IN |
| body_length | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM IN |
| features_provided | HERMETICALLY SEALED AND MONOLITHIC AND NEGATIVE OUTPUTS AND POSITIVE OUTPUTS AND DC COUPLED |
| output_logic_form | TRANSISTOR-TRANSISTOR LOGIC |
| inclosure_material | CERAMIC AND GLASS |
| storage_temp_range | -65.0 TO 150.0 CELSIUS DEGC |
| operating_temp_range | -55.0 TO 125.0 CELSIUS DEGC |
| input_circuit_pattern | 2 INPUT |
| end_item_identification | RADAR SET,TYPE AN/FPS-115 |
| inclosure_configuration | DUAL-IN-LINE |
| terminal_surface_treatment | SOLDER |
| NSN | 5962-01-034-3875 |
| INCLOSURE MATERIAL | CERAMIC |
| TEST DATA DOCUMENT | 81349-MIL-38510,CLASS B SPECIFICATION (INCLUDES ENGINEERING TYPE BULLETINS, BROCHURES,ETC., THAT REFLECT SPECIFICATION TYPE DATA IN SPECIFICATION FORMAT; EXCLUDES COMMERCIAL CATALOGS, INDUSTRY DIRECTORIES, AND SIMILAR TRADE PUBLICATIONS, REFLECTING GENERAL TYPE DATA ON CERTAIN ENVIRONMENTAL AND PERFORMANCE REQUIREMENTS AND TEST CONDITIONS THAT ARE SHOWN AS "TYPICAL", "AVERAGE", "NOMINAL", ETC.). |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| INPUT CIRCUIT PATTERN | 5 INPUT |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| CASE OUTLINE SOURCE AND DESIGNATOR | TO-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 1 DETECTOR, PHASE |
| FEATURES PROVIDED | HERMETICALLY SEALED |
| BODY HEIGHT | 0.200 INCHES NOMINAL IN |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS DEGC |